1. Field of the Invention
The present invention relates to a semiconductor device such as a high voltage transistor used for a semiconductor integrated circuit.
2. Prior Art
High voltage transistors are mostly used as devices constituting driving circuits (drivers) of liquid crystal displays. In recent years, liquid crystal displays have become higher in resolution, decreased in power consumption and increased in screen size, so that higher withstand voltage and lower power consumption have been required of liquid crystal drivers used therefor. In such liquid crystal display drivers, a CMOSFET for a general circuit and a high voltage MOSFET are both provided on the same semiconductor chip, and the circuit configuration is such that the high voltage MOSFET is used as a peripheral circuit connected to an output terminal for output from the semiconductor chip to the outside and the CMOSFET constituting a low-voltage-operated highly integrated circuit that controls the high voltage MOSFET is formed within the semiconductor chip.
The structure of a high voltage transistor having offset-type source and drain used for such circuits is shown in FIGS. 3A to 3D. FIG. 3A is a perspective plan view of the high voltage transistor which is a conventional semiconductor device. FIG. 3B is a cross-sectional view taken on the line III-III′ of FIG. 3A. FIG. 3C is a cross-sectional view taken on the line I-I′ of FIG. 3A. FIG. 3D is a cross-sectional view taken on the line II-II′ of FIG. 3A.
Referring to FIGS. 3B and 3C, a P-type well 2 is present on the surface of a P-type substrate 1. N-type source and drain diffusion layers 3a and 3b, a P-type guard band diffusion layer 4 and a LOCOS oxide film 5 formed by selective oxidation are present on the surface of the P-type well 2. N-type offset diffusion layers 6a and 6b and a P-type diffusion layer 7 are present below the LOCOS oxide film 5. A polysilicon gate electrode 9 is present so as to cover a gate oxide film 8 and part of the LOCOS oxide film 5. The P-type diffusion layer 7 is necessary as a channel stopper region below the LOCOS oxide film 5 of the high voltage transistor.
Referring to FIG. 3A, the N-type offset diffusion layers 6a and 6b are present around the N-type source and drain diffusion layers 3a and 3b of a high impurity concentration and is absent below the gate oxide film 8. The P-type diffusion layer 7 is present in contact with the N-type offset diffusion layers 6a and 6b. The gate oxide film 8 is formed between the source side N-type offset diffusion layer 6a and the drain side N-type offset diffusion layer 6b, and protruding portions 10 outwardly protruding from between the diffusion layers 6a and 6b are present. The P-type diffusion layer 7 is formed inside the P-type guard band diffusion layer 4, is in contact with the N-type offset diffusion layers 6a and 6b, and is also formed below the protruding portions 10 of the gate oxide film 8. This is apparent from the cross-sectional view of FIG. 3C taken on the line I-I′ of FIG. 3A.
The LOCOS oxide film 5 is formed in the region being hatched by broken lines in FIG. 3A, that is, in a region being inside the P-type guard band diffusion layer 4 and excluding the N-type source and drain diffusion layers 3a and 3b and the gate oxide film 8. The conventional high voltage transistor has the structure as described above.
However, the conventional structure has a problem, which will be described below with reference to FIG. 3D. The chain double-dashed line S in FIG. 3D represents the bent part of the line II-II′ of FIG. 3A.
In a case where the high voltage transistor is used as the driver of a liquid crystal panel, for example, when the drain is directly connected to an output pad and the output pad is connected to the liquid crystal panel, the high voltage transistor is capacity-loaded, so that the drain is open. At this time, as shown in FIG. 3D, for example, 0 V is applied to the N-type source diffusion layer 3a, +40 V is applied to the gate electrode 9, −40 V is applied to the P-type well 2 and the P-type guard band diffusion layer 4, and the transistor is on. In the case of such a voltage application condition, an N-type inversion layer 11 is formed immediately below the gate oxide film 8 by the gate voltage. The N-type inversion layer 11 and the P-type diffusion layer 7 form a PN junction 12. Since the N-type source diffusion layer 3a, the N-type offset diffusion layer 6a and the N-type inversion layer 11 are electrically connected, the voltage at the N-type inversion layer 11 is approximately 0 V. It is considered that the potential difference of approximately 40V between −40 V applied to the P-type guard band diffusion layer 4 and 0 V applied to the N-type source diffusion layer 3a is thus applied to the PN junction 12 to cause a tunneling phenomenon that electrons pass through the energy barrier of the PN junction 12, there by causing a leakage current. The arrow B in FIG. 3D represents the path of the leakage current. When the leakage current is caused, in a case where the high voltage transistor is mounted on a liquid crystal panel, an excessive current that does not contribute to the operation flows, which leads to an increase in power consumption. While a case of an N-channel transistor has been described, a similar phenomenon occurs in a P-channel transistor.